`include "ysyx_23060189_cpu.svh"

module ysyx_23060189_RegisterFile (
  input  clk,
  input  wb_en,
  input  wire [`ysyx_23060189_DataBus]    Alu_out,
  input  wire [`ysyx_23060189_DataBus]    csr_out,
  input  wire [`ysyx_23060189_AddrBus]    pc_4,
  input  wire [`ysyx_23060189_WbSelBus]   wb_sel,
  input  wire [`ysyx_23060189_RegAddrBus] wb_addr,
  input  wire [`ysyx_23060189_RegAddrBus] rs1_addr,
  input  wire [`ysyx_23060189_RegAddrBus] rs2_addr,
  input  wire [`ysyx_23060189_DataBus]    rd_data,
  output wire [`ysyx_23060189_DataBus]    rs1_data,
  output wire [`ysyx_23060189_DataBus]    rs2_data
);

  wire [`ysyx_23060189_DataBus]    wb_data;
  reg [`ysyx_23060189_REG_NUM-1:0] rf [`ysyx_23060189_DataBus];

  MuxKey #(4, `ysyx_23060189_WB_SEL_W, `ysyx_23060189_DATA_W) Mux (wb_data, wb_sel, {
    `ysyx_23060189_WB_SEL_PC_4, pc_4,
    `ysyx_23060189_WB_SEL_ALU,  Alu_out,
    `ysyx_23060189_WB_SEL_MEM,  rd_data,
    `ysyx_23060189_WB_SEL_CSR,  csr_out
  });

  assign rs1_data = rs1_addr == 0 ? 0 : rf[rs1_addr];
  assign rs2_data = rs2_addr == 0 ? 0 : rf[rs2_addr];

  always @(posedge clk) begin
    if (wb_en) begin
      if (wb_addr != 0)
        rf[wb_addr] <= wb_data;
    end
  end
endmodule
